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NXP Semiconductors /MKW41Z4 /NVIC /NVIC_ICER

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Interpret as NVIC_ICER

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CLRENA0 0 (0)CLRENA1 0 (0)CLRENA2 0 (0)CLRENA3 0 (0)CLRENA4 0 (0)CLRENA5 0 (0)CLRENA6 0 (0)CLRENA7 0 (0)CLRENA8 0 (0)CLRENA9 0 (0)CLRENA10 0 (0)CLRENA11 0 (0)CLRENA12 0 (0)CLRENA13 0 (0)CLRENA14 0 (0)CLRENA15 0 (0)CLRENA16 0 (0)CLRENA17 0 (0)CLRENA18 0 (0)CLRENA19 0 (0)CLRENA20 0 (0)CLRENA21 0 (0)CLRENA22 0 (0)CLRENA23 0 (0)CLRENA24 0 (0)CLRENA25 0 (0)CLRENA26 0 (0)CLRENA27 0 (0)CLRENA28 0 (0)CLRENA29 0 (0)CLRENA30 0 (0)CLRENA31

CLRENA13=0, CLRENA28=0, CLRENA23=0, CLRENA9=0, CLRENA0=0, CLRENA21=0, CLRENA5=0, CLRENA10=0, CLRENA24=0, CLRENA6=0, CLRENA30=0, CLRENA29=0, CLRENA19=0, CLRENA15=0, CLRENA3=0, CLRENA4=0, CLRENA31=0, CLRENA27=0, CLRENA18=0, CLRENA11=0, CLRENA26=0, CLRENA22=0, CLRENA20=0, CLRENA16=0, CLRENA17=0, CLRENA2=0, CLRENA1=0, CLRENA7=0, CLRENA14=0, CLRENA12=0, CLRENA25=0, CLRENA8=0

Description

Interrupt Clear Enable Register

Fields

CLRENA0

DMA channel 0 transfer complete/error interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 0 transfer complete/error interrupt disabled

1 (1): write: disable DMA channel 0 transfer complete/error interrupt; read: DMA channel 0 transfer complete/error interrupt enabled
CLRENA1

DMA channel 1 transfer complete/error interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 1 transfer complete/error interrupt disabled

1 (1): write: disable DMA channel 1 transfer complete/error interrupt; read: DMA channel 1 transfer complete/error interrupt enabled
CLRENA2

DMA channel 2 transfer complete/error interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 2 transfer complete/error interrupt disabled

1 (1): write: disable DMA channel 2 transfer complete/error interrupt; read: DMA channel 2 transfer complete/error interrupt enabled
CLRENA3

DMA channel 3 transfer complete/error interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 3 transfer complete/error interrupt disabled

1 (1): write: disable DMA channel 3 transfer complete/error interrupt; read: DMA channel 3 transfer complete/error interrupt enabled
CLRENA4

Reserved iv 20 interrupt clear-enable bit

0 (0): write: no effect; read: Reserved iv 20 interrupt disabled

1 (1): write: disable Reserved iv 20 interrupt; read: Reserved iv 20 interrupt enabled
CLRENA5

Flash command complete and read collision interrupt clear-enable bit

0 (0): write: no effect; read: Flash command complete and read collision interrupt disabled

1 (1): write: disable Flash command complete and read collision interrupt; read: Flash command complete and read collision interrupt enabled
CLRENA6

Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt clear-enable bit

0 (0): write: no effect; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt disabled

1 (1): write: disable Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt; read: Low-voltage detect, low-voltage warning and DCDC PSWITCH interrupt interrupt enabled
CLRENA7

Low Leakage Wakeup interrupt clear-enable bit

0 (0): write: no effect; read: Low Leakage Wakeup interrupt disabled

1 (1): write: disable Low Leakage Wakeup interrupt; read: Low Leakage Wakeup interrupt enabled
CLRENA8

Inter-Integrated Circuit 0 interrupt clear-enable bit

0 (0): write: no effect; read: Inter-Integrated Circuit 0 interrupt disabled

1 (1): write: disable Inter-Integrated Circuit 0 interrupt; read: Inter-Integrated Circuit 0 interrupt enabled
CLRENA9

Inter-Integrated Circuit 1 interrupt clear-enable bit

0 (0): write: no effect; read: Inter-Integrated Circuit 1 interrupt disabled

1 (1): write: disable Inter-Integrated Circuit 1 interrupt; read: Inter-Integrated Circuit 1 interrupt enabled
CLRENA10

Serial Peripheral Interface 0 interrupt clear-enable bit

0 (0): write: no effect; read: Serial Peripheral Interface 0 interrupt disabled

1 (1): write: disable Serial Peripheral Interface 0 interrupt; read: Serial Peripheral Interface 0 interrupt enabled
CLRENA11

Touch Sensing Input interrupt clear-enable bit

0 (0): write: no effect; read: Touch Sensing Input interrupt disabled

1 (1): write: disable Touch Sensing Input interrupt; read: Touch Sensing Input interrupt enabled
CLRENA12

LPUART0 status and error interrupt clear-enable bit

0 (0): write: no effect; read: LPUART0 status and error interrupt disabled

1 (1): write: disable LPUART0 status and error interrupt; read: LPUART0 status and error interrupt enabled
CLRENA13

True Random Number Generator interrupt clear-enable bit

0 (0): write: no effect; read: True Random Number Generator interrupt disabled

1 (1): write: disable True Random Number Generator interrupt; read: True Random Number Generator interrupt enabled
CLRENA14

Carrier modulator transmitter interrupt clear-enable bit

0 (0): write: no effect; read: Carrier modulator transmitter interrupt disabled

1 (1): write: disable Carrier modulator transmitter interrupt; read: Carrier modulator transmitter interrupt enabled
CLRENA15

Analog-to-Digital Converter 0 interrupt clear-enable bit

0 (0): write: no effect; read: Analog-to-Digital Converter 0 interrupt disabled

1 (1): write: disable Analog-to-Digital Converter 0 interrupt; read: Analog-to-Digital Converter 0 interrupt enabled
CLRENA16

DMA channel 0 - 31 error interrupt clear-enable bit

0 (0): write: no effect; read: DMA channel 0 - 31 error interrupt disabled

1 (1): write: disable DMA channel 0 - 31 error interrupt; read: DMA channel 0 - 31 error interrupt enabled
CLRENA17

Timer/PWM module 0 interrupt clear-enable bit

0 (0): write: no effect; read: Timer/PWM module 0 interrupt disabled

1 (1): write: disable Timer/PWM module 0 interrupt; read: Timer/PWM module 0 interrupt enabled
CLRENA18

Timer/PWM module 1 interrupt clear-enable bit

0 (0): write: no effect; read: Timer/PWM module 1 interrupt disabled

1 (1): write: disable Timer/PWM module 1 interrupt; read: Timer/PWM module 1 interrupt enabled
CLRENA19

Timer/PWM module 2 interrupt clear-enable bit

0 (0): write: no effect; read: Timer/PWM module 2 interrupt disabled

1 (1): write: disable Timer/PWM module 2 interrupt; read: Timer/PWM module 2 interrupt enabled
CLRENA20

Real-time counter interrupt clear-enable bit

0 (0): write: no effect; read: Real-time counter interrupt disabled

1 (1): write: disable Real-time counter interrupt; read: Real-time counter interrupt enabled
CLRENA21

RTC seconds interrupt clear-enable bit

0 (0): write: no effect; read: RTC seconds interrupt disabled

1 (1): write: disable RTC seconds interrupt; read: RTC seconds interrupt enabled
CLRENA22

Periodic Interrupt Timer interrupt clear-enable bit

0 (0): write: no effect; read: Periodic Interrupt Timer interrupt disabled

1 (1): write: disable Periodic Interrupt Timer interrupt; read: Periodic Interrupt Timer interrupt enabled
CLRENA23

LTC0 interrupt clear-enable bit

0 (0): write: no effect; read: LTC0 interrupt disabled

1 (1): write: disable LTC0 interrupt; read: LTC0 interrupt enabled
CLRENA24

Radio 0 interrupt clear-enable bit

0 (0): write: no effect; read: Radio 0 interrupt disabled

1 (1): write: disable Radio 0 interrupt; read: Radio 0 interrupt enabled
CLRENA25

Digital to Analog Converter interrupt clear-enable bit

0 (0): write: no effect; read: Digital to Analog Converter interrupt disabled

1 (1): write: disable Digital to Analog Converter interrupt; read: Digital to Analog Converter interrupt enabled
CLRENA26

Radio 1 interrupt clear-enable bit

0 (0): write: no effect; read: Radio 1 interrupt disabled

1 (1): write: disable Radio 1 interrupt; read: Radio 1 interrupt enabled
CLRENA27

Multipurpose Clock Generator interrupt clear-enable bit

0 (0): write: no effect; read: Multipurpose Clock Generator interrupt disabled

1 (1): write: disable Multipurpose Clock Generator interrupt; read: Multipurpose Clock Generator interrupt enabled
CLRENA28

Low-Power Timer 0 interrupt clear-enable bit

0 (0): write: no effect; read: Low-Power Timer 0 interrupt disabled

1 (1): write: disable Low-Power Timer 0 interrupt; read: Low-Power Timer 0 interrupt enabled
CLRENA29

Serial Peripheral Interface 1 interrupt clear-enable bit

0 (0): write: no effect; read: Serial Peripheral Interface 1 interrupt disabled

1 (1): write: disable Serial Peripheral Interface 1 interrupt; read: Serial Peripheral Interface 1 interrupt enabled
CLRENA30

Pin detect Port A interrupt clear-enable bit

0 (0): write: no effect; read: Pin detect Port A interrupt disabled

1 (1): write: disable Pin detect Port A interrupt; read: Pin detect Port A interrupt enabled
CLRENA31

Pin detect Port B and C interrupt clear-enable bit

0 (0): write: no effect; read: Pin detect Port B and C interrupt disabled

1 (1): write: disable Pin detect Port B and C interrupt; read: Pin detect Port B and C interrupt enabled

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of the copyright holder nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data